This invention relates to Complementary Metal Oxide Semiconductor (CMOS) low noise amplifiers (LNA).
One of the key building blocks of a conventional RF transceiver is a Low Noise Amplifier (LNA). FIG. 1 shows an implementation of a CMOS LNA high gain path 200 commonly adopted in conventional RF transceivers. The gain of this amplifier can be expressed as:
Av=gmxc2x7Q2xc2x7Rp where gm is the transconductance of the input device, Q is the quality factor of the load inductor and Rp is the parasitic resistance associated with the inductor.
Referring to the equation above, the gain is a strong function of gm of the input transistor, as well as the Q of the inductor of the LNA. gm may vary +/xe2x88x9230-40%, and the Q2Rp term typically varies +/xe2x88x9210-20% due to process, temperature etc. variation. As a result, the gain of the LNA can easily vary by greater than 6 dB. This gain variation may affect receiver performance significantly in real life applications and hence, the implementation may not be desirable.
An amplifier comprising a Low Noise Amplifier (LNA) to amplify a Radio Frequency (RF) signal. The gain of the LNA varying as a function of changes in the process and environmental conditions. A bias assembly to generate a bias current to bias the LNA input stage. The bias assembly configured to reduce the variation of the LNA gain due to changes in process variations and environmental conditions.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.